1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor memory device provided with mode register units.
2. Description of the Related Art
In general, a semiconductor memory device such as a double data rate synchronous DRAM (DDR SDRAM) is provided with mode register units, wherein the mode register units store information of device operation, such as CAS latency, column address strobe latency, a bust type, a burst length, a bank grouping mode, and DLL on/off. The mode register units store corresponding information before the semiconductor memory device operates, and the semiconductor memory device is set with the stored information. The information data stored in the mode register units is input through address pins, and will be referred to as address signals ADD for the purpose of convenience.
FIG. 1 is a block diagram for explaining a partial configuration of a conventional semiconductor memory device.
Referring to FIG. 1, the semiconductor memory device includes a command decoding unit 110, a mode register activation control unit 120, and first to fourth mode register units 130_1 to 130_4.
The command decoding unit 110 generates a mode register enable signal EN in response to a plurality of command signals CMD, and the mode register activation control unit 120 generates first to fourth mode register activation signals EN_MRS1 to EN_MRS4 corresponding to a plurality of bank address signals BA in response to the mode register enable signal EN. The mode register enable signal EN is activated when the command signals CMD is input to the command decoding unit 110 with a given value corresponding to a mode register units operation, and the bank address signals BA are used to select the first to fourth mode register units 130_1 to 130_4.
The first to fourth mode register units 130_1 to 130_4 store address signals ADD in response to the first to fourth mode register activation signals EN_MRS1 to EN_MRS4, respectively. Data stored in the first to fourth mode register units units 130_1 to 130_4 is used as the aforementioned information on CAS latency, a bust type, a burst length, a bank grouping mode, DLL on/off, and the like.
FIG. 2 is an operation waveform diagram for illustrating the operation of the semiconductor memory device of FIG. 1. Hereinafter, the operation of the semiconductor memory device will be described with reference to FIG. 1 and FIG. 2.
The command decoding unit 110 decodes the command signals CMD and activates the mode register enable signal EN. In general, the bank address signals BA and the address signals ADD are input at substantially the same time as that of the command signals CMD. The mode register activation control unit 120 activates a mode register activation signal corresponding to the bank address signals BA of the first to fourth mode register activation signals EN_MRS1 to EN_MRS4 in response to the bank address signals BA and the mode register enable signal EN. The first to fourth mode register units 130_1 to 130_4 receive and store the address signals ADD in response to the first to fourth mode register activation signals EN_MRS1 to EN_MRS4, and decode the stored data to output first to fourth mode register output signals OUT_MRS1 to OUT_MRS4, respectively.
Meanwhile, a predetermined time is required for the first to fourth mode register units 130_1 to 130_4 to receive and store the address signals ADD. In other words, the first mode register unit 130_1 receives a first address signal ADD1 (refer to FIG. 2) corresponding to the first mode register unit 130_1 in response to the first mode register activation signal EN_MRS1, and decodes the received first address signal ADD1 to output the first mode register output signal OUT_MRS1 after a predetermined time lapses. A second address signal ADD2 corresponding to the second mode register unit 130_2 should be input after the first mode register output signal OUT_MRS1 is output. This is applied to third and fourth address signals ADD3 and ADD4 in the same manner.
Accordingly, to stably store the address signals ADD in the first to fourth mode register units 130_1 to 130_4, it is necessary to input the first to fourth address signals ADD1 to ADD4 in consideration of data storage completion times of the first to fourth mode register units 130_1 to 130_4. This is because input times of the first to fourth address signals ADD1 to ADD4 are limited due to the storage completion times of the first to fourth mode register units 130_1 to 130_4.
Recently, a semiconductor memory device operates at a higher speed. However, obtaining a high speed operation of the semiconductor memory device may be hindered by data storage completion times of mode registers.